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    <h1>File: /Users/paulross/dev/linux/linux-3.13/arch/x86/include/asm/irq_vectors.h</h1>
    <p>Green shading in the line number column
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    <pre><a name="1" /><span class="Maybe">       1:</span> <span class="f">#</span><span class="n">ifndef</span> <a href="cpu.c_macros_ref.html#_X0FTTV9YODZfSVJRX1ZFQ1RPUlNfSF8w"><span class="b">_ASM_X86_IRQ_VECTORS_H</span></a>
<a name="2" /><span class="Maybe">       2:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_X0FTTV9YODZfSVJRX1ZFQ1RPUlNfSF8w"><span class="b">_ASM_X86_IRQ_VECTORS_H</span></a>
<a name="3" /><span class="Maybe">       3:</span> 
<a name="4" /><span class="Maybe">       4:</span> <span class="f">#</span><span class="n">include</span> <span class="f">&lt;</span><span class="b">linux</span><span class="f">/</span><span class="b">threads</span><span class="f">.</span><span class="b">h</span><span class="f">&gt;</span>
<a name="5" /><span class="Maybe">       5:</span> <span class="k">/*</span>
<a name="6" /><span class="Maybe">       6:</span> <span class="k"> * Linux IRQ vector layout.</span>
<a name="7" /><span class="Maybe">       7:</span> <span class="k"> *</span>
<a name="8" /><span class="Maybe">       8:</span> <span class="k"> * There are 256 IDT entries (per CPU - each entry is 8 bytes) which can</span>
<a name="9" /><span class="Maybe">       9:</span> <span class="k"> * be defined by Linux. They are used as a jump table by the CPU when a</span>
<a name="10" /><span class="Maybe">      10:</span> <span class="k"> * given vector is triggered - by a CPU-external, CPU-internal or</span>
<a name="11" /><span class="Maybe">      11:</span> <span class="k"> * software-triggered event.</span>
<a name="12" /><span class="Maybe">      12:</span> <span class="k"> *</span>
<a name="13" /><span class="Maybe">      13:</span> <span class="k"> * Linux sets the kernel code address each entry jumps to early during</span>
<a name="14" /><span class="Maybe">      14:</span> <span class="k"> * bootup, and never changes them. This is the general layout of the</span>
<a name="15" /><span class="Maybe">      15:</span> <span class="k"> * IDT entries:</span>
<a name="16" /><span class="Maybe">      16:</span> <span class="k"> *</span>
<a name="17" /><span class="Maybe">      17:</span> <span class="k"> *  Vectors   0 ...  31 : system traps and exceptions - hardcoded events</span>
<a name="18" /><span class="Maybe">      18:</span> <span class="k"> *  Vectors  32 ... 127 : device interrupts</span>
<a name="19" /><span class="Maybe">      19:</span> <span class="k"> *  Vector  128         : legacy int80 syscall interface</span>
<a name="20" /><span class="Maybe">      20:</span> <span class="k"> *  Vectors 129 ... INVALIDATE_TLB_VECTOR_START-1 except 204 : device interrupts</span>
<a name="21" /><span class="Maybe">      21:</span> <span class="k"> *  Vectors INVALIDATE_TLB_VECTOR_START ... 255 : special interrupts</span>
<a name="22" /><span class="Maybe">      22:</span> <span class="k"> *</span>
<a name="23" /><span class="Maybe">      23:</span> <span class="k"> * 64-bit x86 has per CPU IDT tables, 32-bit has one shared IDT table.</span>
<a name="24" /><span class="Maybe">      24:</span> <span class="k"> *</span>
<a name="25" /><span class="Maybe">      25:</span> <span class="k"> * This file enumerates the exact layout of them:</span>
<a name="26" /><span class="Maybe">      26:</span> <span class="k"> */</span>
<a name="27" /><span class="Maybe">      27:</span> 
<a name="28" /><span class="Maybe">      28:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Tk1JX1ZFQ1RPUl8w"><span class="b">NMI_VECTOR</span></a>            <span class="c">0x02</span>
<a name="29" /><span class="Maybe">      29:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TUNFX1ZFQ1RPUl8w"><span class="b">MCE_VECTOR</span></a>            <span class="c">0x12</span>
<a name="30" /><span class="Maybe">      30:</span> 
<a name="31" /><span class="Maybe">      31:</span> <span class="k">/*</span>
<a name="32" /><span class="Maybe">      32:</span> <span class="k"> * IDT vectors usable for external interrupt sources start at 0x20.</span>
<a name="33" /><span class="Maybe">      33:</span> <span class="k"> * (0x80 is the syscall vector, 0x30-0x3f are for ISA)</span>
<a name="34" /><span class="Maybe">      34:</span> <span class="k"> */</span>
<a name="35" /><span class="Maybe">      35:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_RklSU1RfRVhURVJOQUxfVkVDVE9SXzA_"><span class="b">FIRST_EXTERNAL_VECTOR</span></a>        <span class="c">0x20</span>
<a name="36" /><span class="Maybe">      36:</span> <span class="k">/*</span>
<a name="37" /><span class="Maybe">      37:</span> <span class="k"> * We start allocating at 0x21 to spread out vectors evenly between</span>
<a name="38" /><span class="Maybe">      38:</span> <span class="k"> * priority levels. (0x80 is the syscall vector)</span>
<a name="39" /><span class="Maybe">      39:</span> <span class="k"> */</span>
<a name="40" /><span class="Maybe">      40:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_VkVDVE9SX09GRlNFVF9TVEFSVF8w"><span class="b">VECTOR_OFFSET_START</span></a>        <span class="c">1</span>
<a name="41" /><span class="Maybe">      41:</span> 
<a name="42" /><span class="Maybe">      42:</span> <span class="k">/*</span>
<a name="43" /><span class="Maybe">      43:</span> <span class="k"> * Reserve the lowest usable vector (and hence lowest priority)  0x20 for</span>
<a name="44" /><span class="Maybe">      44:</span> <span class="k"> * triggering cleanup after irq migration. 0x21-0x2f will still be used</span>
<a name="45" /><span class="Maybe">      45:</span> <span class="k"> * for device interrupts.</span>
<a name="46" /><span class="Maybe">      46:</span> <span class="k"> */</span>
<a name="47" /><span class="Maybe">      47:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_SVJRX01PVkVfQ0xFQU5VUF9WRUNUT1JfMA__"><span class="b">IRQ_MOVE_CLEANUP_VECTOR</span></a>        <a href="cpu.c_macros_ref.html#_RklSU1RfRVhURVJOQUxfVkVDVE9SXzA_"><span class="b">FIRST_EXTERNAL_VECTOR</span></a>
<a name="48" /><span class="Maybe">      48:</span> 
<a name="49" /><span class="Maybe">      49:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_SUEzMl9TWVNDQUxMX1ZFQ1RPUl8w"><span class="b">IA32_SYSCALL_VECTOR</span></a>        <span class="c">0x80</span>
<a name="50" /><span class="False">      50:</span> <span class="f">#</span><span class="n">ifdef</span> <span class="b">CONFIG_X86_32</span>
<a name="51" /><span class="False">      51:</span> <span class="f">#</span> <span class="n">define</span> <span class="b">SYSCALL_VECTOR</span>            <span class="c">0x80</span>
<a name="52" /><span class="Maybe">      52:</span> <span class="f">#</span><span class="n">endif</span>
<a name="53" /><span class="Maybe">      53:</span> 
<a name="54" /><span class="Maybe">      54:</span> <span class="k">/*</span>
<a name="55" /><span class="Maybe">      55:</span> <span class="k"> * Vectors 0x30-0x3f are used for ISA interrupts.</span>
<a name="56" /><span class="Maybe">      56:</span> <span class="k"> *   round up to the next 16-vector boundary</span>
<a name="57" /><span class="Maybe">      57:</span> <span class="k"> */</span>
<a name="58" /><span class="Maybe">      58:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_SVJRMF9WRUNUT1JfMA__"><span class="b">IRQ0_VECTOR</span></a>            <span class="f">(</span><span class="f">(</span><a href="cpu.c_macros_ref.html#_RklSU1RfRVhURVJOQUxfVkVDVE9SXzA_"><span class="b">FIRST_EXTERNAL_VECTOR</span></a> <span class="f">+</span> <span class="c">16</span><span class="f">)</span> <span class="f">&amp;</span> <span class="f">~</span><span class="c">15</span><span class="f">)</span>
<a name="59" /><span class="Maybe">      59:</span> 
<a name="60" /><span class="Maybe">      60:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_SVJRMV9WRUNUT1JfMA__"><span class="b">IRQ1_VECTOR</span></a>            <span class="f">(</span><a href="cpu.c_macros_noref.html#_SVJRMF9WRUNUT1JfMA__"><span class="b">IRQ0_VECTOR</span></a> <span class="f">+</span>  <span class="c">1</span><span class="f">)</span>
<a name="61" /><span class="Maybe">      61:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_SVJRMl9WRUNUT1JfMA__"><span class="b">IRQ2_VECTOR</span></a>            <span class="f">(</span><a href="cpu.c_macros_noref.html#_SVJRMF9WRUNUT1JfMA__"><span class="b">IRQ0_VECTOR</span></a> <span class="f">+</span>  <span class="c">2</span><span class="f">)</span>
<a name="62" /><span class="Maybe">      62:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_SVJRM19WRUNUT1JfMA__"><span class="b">IRQ3_VECTOR</span></a>            <span class="f">(</span><a href="cpu.c_macros_noref.html#_SVJRMF9WRUNUT1JfMA__"><span class="b">IRQ0_VECTOR</span></a> <span class="f">+</span>  <span class="c">3</span><span class="f">)</span>
<a name="63" /><span class="Maybe">      63:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_SVJRNF9WRUNUT1JfMA__"><span class="b">IRQ4_VECTOR</span></a>            <span class="f">(</span><a href="cpu.c_macros_noref.html#_SVJRMF9WRUNUT1JfMA__"><span class="b">IRQ0_VECTOR</span></a> <span class="f">+</span>  <span class="c">4</span><span class="f">)</span>
<a name="64" /><span class="Maybe">      64:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_SVJRNV9WRUNUT1JfMA__"><span class="b">IRQ5_VECTOR</span></a>            <span class="f">(</span><a href="cpu.c_macros_noref.html#_SVJRMF9WRUNUT1JfMA__"><span class="b">IRQ0_VECTOR</span></a> <span class="f">+</span>  <span class="c">5</span><span class="f">)</span>
<a name="65" /><span class="Maybe">      65:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_SVJRNl9WRUNUT1JfMA__"><span class="b">IRQ6_VECTOR</span></a>            <span class="f">(</span><a href="cpu.c_macros_noref.html#_SVJRMF9WRUNUT1JfMA__"><span class="b">IRQ0_VECTOR</span></a> <span class="f">+</span>  <span class="c">6</span><span class="f">)</span>
<a name="66" /><span class="Maybe">      66:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_SVJRN19WRUNUT1JfMA__"><span class="b">IRQ7_VECTOR</span></a>            <span class="f">(</span><a href="cpu.c_macros_noref.html#_SVJRMF9WRUNUT1JfMA__"><span class="b">IRQ0_VECTOR</span></a> <span class="f">+</span>  <span class="c">7</span><span class="f">)</span>
<a name="67" /><span class="Maybe">      67:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_SVJROF9WRUNUT1JfMA__"><span class="b">IRQ8_VECTOR</span></a>            <span class="f">(</span><a href="cpu.c_macros_noref.html#_SVJRMF9WRUNUT1JfMA__"><span class="b">IRQ0_VECTOR</span></a> <span class="f">+</span>  <span class="c">8</span><span class="f">)</span>
<a name="68" /><span class="Maybe">      68:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_SVJROV9WRUNUT1JfMA__"><span class="b">IRQ9_VECTOR</span></a>            <span class="f">(</span><a href="cpu.c_macros_noref.html#_SVJRMF9WRUNUT1JfMA__"><span class="b">IRQ0_VECTOR</span></a> <span class="f">+</span>  <span class="c">9</span><span class="f">)</span>
<a name="69" /><span class="Maybe">      69:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_SVJRMTBfVkVDVE9SXzA_"><span class="b">IRQ10_VECTOR</span></a>            <span class="f">(</span><a href="cpu.c_macros_noref.html#_SVJRMF9WRUNUT1JfMA__"><span class="b">IRQ0_VECTOR</span></a> <span class="f">+</span> <span class="c">10</span><span class="f">)</span>
<a name="70" /><span class="Maybe">      70:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_SVJRMTFfVkVDVE9SXzA_"><span class="b">IRQ11_VECTOR</span></a>            <span class="f">(</span><a href="cpu.c_macros_noref.html#_SVJRMF9WRUNUT1JfMA__"><span class="b">IRQ0_VECTOR</span></a> <span class="f">+</span> <span class="c">11</span><span class="f">)</span>
<a name="71" /><span class="Maybe">      71:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_SVJRMTJfVkVDVE9SXzA_"><span class="b">IRQ12_VECTOR</span></a>            <span class="f">(</span><a href="cpu.c_macros_noref.html#_SVJRMF9WRUNUT1JfMA__"><span class="b">IRQ0_VECTOR</span></a> <span class="f">+</span> <span class="c">12</span><span class="f">)</span>
<a name="72" /><span class="Maybe">      72:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_SVJRMTNfVkVDVE9SXzA_"><span class="b">IRQ13_VECTOR</span></a>            <span class="f">(</span><a href="cpu.c_macros_noref.html#_SVJRMF9WRUNUT1JfMA__"><span class="b">IRQ0_VECTOR</span></a> <span class="f">+</span> <span class="c">13</span><span class="f">)</span>
<a name="73" /><span class="Maybe">      73:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_SVJRMTRfVkVDVE9SXzA_"><span class="b">IRQ14_VECTOR</span></a>            <span class="f">(</span><a href="cpu.c_macros_noref.html#_SVJRMF9WRUNUT1JfMA__"><span class="b">IRQ0_VECTOR</span></a> <span class="f">+</span> <span class="c">14</span><span class="f">)</span>
<a name="74" /><span class="Maybe">      74:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_SVJRMTVfVkVDVE9SXzA_"><span class="b">IRQ15_VECTOR</span></a>            <span class="f">(</span><a href="cpu.c_macros_noref.html#_SVJRMF9WRUNUT1JfMA__"><span class="b">IRQ0_VECTOR</span></a> <span class="f">+</span> <span class="c">15</span><span class="f">)</span>
<a name="75" /><span class="Maybe">      75:</span> 
<a name="76" /><span class="Maybe">      76:</span> <span class="k">/*</span>
<a name="77" /><span class="Maybe">      77:</span> <span class="k"> * Special IRQ vectors used by the SMP architecture, 0xf0-0xff</span>
<a name="78" /><span class="Maybe">      78:</span> <span class="k"> *</span>
<a name="79" /><span class="Maybe">      79:</span> <span class="k"> *  some of the following vectors are &apos;rare&apos;, they are merged</span>
<a name="80" /><span class="Maybe">      80:</span> <span class="k"> *  into a single vector (CALL_FUNCTION_VECTOR) to save vector space.</span>
<a name="81" /><span class="Maybe">      81:</span> <span class="k"> *  TLB, reschedule and local APIC vectors are performance-critical.</span>
<a name="82" /><span class="Maybe">      82:</span> <span class="k"> */</span>
<a name="83" /><span class="Maybe">      83:</span> 
<a name="84" /><span class="Maybe">      84:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_U1BVUklPVVNfQVBJQ19WRUNUT1JfMA__"><span class="b">SPURIOUS_APIC_VECTOR</span></a>        <span class="c">0xff</span>
<a name="85" /><span class="Maybe">      85:</span> <span class="k">/*</span>
<a name="86" /><span class="Maybe">      86:</span> <span class="k"> * Sanity check</span>
<a name="87" /><span class="Maybe">      87:</span> <span class="k"> */</span>
<a name="88" /><span class="False">      88:</span> <span class="f">#</span><span class="n">if</span> <span class="f">(</span><span class="f">(</span><a href="cpu.c_macros_ref.html#_U1BVUklPVVNfQVBJQ19WRUNUT1JfMA__"><span class="b">SPURIOUS_APIC_VECTOR</span></a> <span class="f">&amp;</span> <span class="c">0x0F</span><span class="f">)</span> <span class="f">!=</span> <span class="c">0x0F</span><span class="f">)</span>
<a name="89" /><span class="False">      89:</span> <span class="f">#</span> <span class="n">error</span> <a href="cpu.c_macros_ref.html#_U1BVUklPVVNfQVBJQ19WRUNUT1JfMA__"><span class="b">SPURIOUS_APIC_VECTOR</span></a> <span class="b">definition</span> <span class="b">error</span>
<a name="90" /><span class="Maybe">      90:</span> <span class="f">#</span><span class="n">endif</span>
<a name="91" /><span class="Maybe">      91:</span> 
<a name="92" /><span class="Maybe">      92:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_RVJST1JfQVBJQ19WRUNUT1JfMA__"><span class="b">ERROR_APIC_VECTOR</span></a>        <span class="c">0xfe</span>
<a name="93" /><span class="Maybe">      93:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_UkVTQ0hFRFVMRV9WRUNUT1JfMA__"><span class="b">RESCHEDULE_VECTOR</span></a>        <span class="c">0xfd</span>
<a name="94" /><span class="Maybe">      94:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Q0FMTF9GVU5DVElPTl9WRUNUT1JfMA__"><span class="b">CALL_FUNCTION_VECTOR</span></a>        <span class="c">0xfc</span>
<a name="95" /><span class="Maybe">      95:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_Q0FMTF9GVU5DVElPTl9TSU5HTEVfVkVDVE9SXzA_"><span class="b">CALL_FUNCTION_SINGLE_VECTOR</span></a>    <span class="c">0xfb</span>
<a name="96" /><span class="Maybe">      96:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_VEhFUk1BTF9BUElDX1ZFQ1RPUl8w"><span class="b">THERMAL_APIC_VECTOR</span></a>        <span class="c">0xfa</span>
<a name="97" /><span class="Maybe">      97:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_VEhSRVNIT0xEX0FQSUNfVkVDVE9SXzA_"><span class="b">THRESHOLD_APIC_VECTOR</span></a>        <span class="c">0xf9</span>
<a name="98" /><span class="Maybe">      98:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_UkVCT09UX1ZFQ1RPUl8w"><span class="b">REBOOT_VECTOR</span></a>            <span class="c">0xf8</span>
<a name="99" /><span class="Maybe">      99:</span> 
<a name="100" /><span class="Maybe">     100:</span> <span class="k">/*</span>
<a name="101" /><span class="Maybe">     101:</span> <span class="k"> * Generic system vector for platform specific use</span>
<a name="102" /><span class="Maybe">     102:</span> <span class="k"> */</span>
<a name="103" /><span class="Maybe">     103:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_WDg2X1BMQVRGT1JNX0lQSV9WRUNUT1JfMA__"><span class="b">X86_PLATFORM_IPI_VECTOR</span></a>        <span class="c">0xf7</span>
<a name="104" /><span class="Maybe">     104:</span> 
<a name="105" /><span class="Maybe">     105:</span> <span class="k">/* Vector for KVM to deliver posted interrupt IPI */</span>
<a name="106" /><span class="Maybe">     106:</span> <span class="f">#</span><span class="n">ifdef</span> <a href="cpu.c_macros_ref.html#_Q09ORklHX0hBVkVfS1ZNXzA_"><span class="b">CONFIG_HAVE_KVM</span></a>
<a name="107" /><span class="Maybe">     107:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_UE9TVEVEX0lOVFJfVkVDVE9SXzA_"><span class="b">POSTED_INTR_VECTOR</span></a>        <span class="c">0xf2</span>
<a name="108" /><span class="Maybe">     108:</span> <span class="f">#</span><span class="n">endif</span>
<a name="109" /><span class="Maybe">     109:</span> 
<a name="110" /><span class="Maybe">     110:</span> <span class="k">/*</span>
<a name="111" /><span class="Maybe">     111:</span> <span class="k"> * IRQ work vector:</span>
<a name="112" /><span class="Maybe">     112:</span> <span class="k"> */</span>
<a name="113" /><span class="Maybe">     113:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_SVJRX1dPUktfVkVDVE9SXzA_"><span class="b">IRQ_WORK_VECTOR</span></a>            <span class="c">0xf6</span>
<a name="114" /><span class="Maybe">     114:</span> 
<a name="115" /><span class="Maybe">     115:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_VVZfQkFVX01FU1NBR0VfMA__"><span class="b">UV_BAU_MESSAGE</span></a>            <span class="c">0xf5</span>
<a name="116" /><span class="Maybe">     116:</span> 
<a name="117" /><span class="Maybe">     117:</span> <span class="k">/* Vector on which hypervisor callbacks will be delivered */</span>
<a name="118" /><span class="Maybe">     118:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_SFlQRVJWSVNPUl9DQUxMQkFDS19WRUNUT1JfMA__"><span class="b">HYPERVISOR_CALLBACK_VECTOR</span></a>    <span class="c">0xf3</span>
<a name="119" /><span class="Maybe">     119:</span> 
<a name="120" /><span class="Maybe">     120:</span> <span class="k">/*</span>
<a name="121" /><span class="Maybe">     121:</span> <span class="k"> * Local APIC timer IRQ vector is on a different priority level,</span>
<a name="122" /><span class="Maybe">     122:</span> <span class="k"> * to work around the &apos;lost local interrupt if more than 2 IRQ</span>
<a name="123" /><span class="Maybe">     123:</span> <span class="k"> * sources per level&apos; errata.</span>
<a name="124" /><span class="Maybe">     124:</span> <span class="k"> */</span>
<a name="125" /><span class="Maybe">     125:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_TE9DQUxfVElNRVJfVkVDVE9SXzA_"><span class="b">LOCAL_TIMER_VECTOR</span></a>        <span class="c">0xef</span>
<a name="126" /><span class="Maybe">     126:</span> 
<a name="127" /><span class="Maybe">     127:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_TlJfVkVDVE9SU18w"><span class="b">NR_VECTORS</span></a>             <span class="c">256</span>
<a name="128" /><span class="Maybe">     128:</span> 
<a name="129" /><span class="Maybe">     129:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_RlBVX0lSUV8w"><span class="b">FPU_IRQ</span></a>                  <span class="c">13</span>
<a name="130" /><span class="Maybe">     130:</span> 
<a name="131" /><span class="Maybe">     131:</span> <span class="f">#</span><span class="n">define</span>    <a href="cpu.c_macros_ref.html#_RklSU1RfVk04Nl9JUlFfMA__"><span class="b">FIRST_VM86_IRQ</span></a>               <span class="c">3</span>
<a name="132" /><span class="Maybe">     132:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_TEFTVF9WTTg2X0lSUV8w"><span class="b">LAST_VM86_IRQ</span></a>              <span class="c">15</span>
<a name="133" /><span class="Maybe">     133:</span> 
<a name="134" /><span class="Maybe">     134:</span> <span class="f">#</span><span class="n">ifndef</span> <span class="b">__ASSEMBLY__</span>
<a name="135" /><span class="Maybe">     135:</span> <span class="m">static</span> <span class="m">inline</span> <span class="m">int</span> <span class="b">invalid_vm86_irq</span><span class="f">(</span><span class="m">int</span> <span class="b">irq</span><span class="f">)</span>
<a name="136" /><span class="Maybe">     136:</span> <span class="f">{</span>
<a name="137" /><span class="Maybe">     137:</span>     <span class="m">return</span> <span class="b">irq</span> <span class="f">&lt;</span> <a href="cpu.c_macros_ref.html#_RklSU1RfVk04Nl9JUlFfMA__"><span class="b">FIRST_VM86_IRQ</span></a> <span class="f">||</span> <span class="b">irq</span> <span class="f">&gt;</span> <a href="cpu.c_macros_ref.html#_TEFTVF9WTTg2X0lSUV8w"><span class="b">LAST_VM86_IRQ</span></a><span class="f">;</span>
<a name="138" /><span class="Maybe">     138:</span> <span class="f">}</span>
<a name="139" /><span class="Maybe">     139:</span> <span class="f">#</span><span class="n">endif</span>
<a name="140" /><span class="Maybe">     140:</span> 
<a name="141" /><span class="Maybe">     141:</span> <span class="k">/*</span>
<a name="142" /><span class="Maybe">     142:</span> <span class="k"> * Size the maximum number of interrupts.</span>
<a name="143" /><span class="Maybe">     143:</span> <span class="k"> *</span>
<a name="144" /><span class="Maybe">     144:</span> <span class="k"> * If the irq_desc[] array has a sparse layout, we can size things</span>
<a name="145" /><span class="Maybe">     145:</span> <span class="k"> * generously - it scales up linearly with the maximum number of CPUs,</span>
<a name="146" /><span class="Maybe">     146:</span> <span class="k"> * and the maximum number of IO-APICs, whichever is higher.</span>
<a name="147" /><span class="Maybe">     147:</span> <span class="k"> *</span>
<a name="148" /><span class="Maybe">     148:</span> <span class="k"> * In other cases we size more conservatively, to not create too large</span>
<a name="149" /><span class="Maybe">     149:</span> <span class="k"> * static arrays.</span>
<a name="150" /><span class="Maybe">     150:</span> <span class="k"> */</span>
<a name="151" /><span class="Maybe">     151:</span> 
<a name="152" /><span class="Maybe">     152:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_ref.html#_TlJfSVJRU19MRUdBQ1lfMA__"><span class="b">NR_IRQS_LEGACY</span></a>              <span class="c">16</span>
<a name="153" /><span class="Maybe">     153:</span> 
<a name="154" /><span class="Maybe">     154:</span> <span class="f">#</span><span class="n">define</span> <a href="cpu.c_macros_noref.html#_SU9fQVBJQ19WRUNUT1JfTElNSVRfMA__"><span class="b">IO_APIC_VECTOR_LIMIT</span></a>        <span class="f">(</span> <span class="c">32</span> <span class="f">*</span> <a href="cpu.c_macros_ref.html#_TUFYX0lPX0FQSUNTXzA_"><span class="b">MAX_IO_APICS</span></a> <span class="f">)</span>
<a name="155" /><span class="Maybe">     155:</span> 
<a name="156" /><span class="Maybe">     156:</span> <span class="f">#</span><span class="n">ifdef</span> <a href="cpu.c_macros_ref.html#_Q09ORklHX1g4Nl9JT19BUElDXzA_"><span class="b">CONFIG_X86_IO_APIC</span></a>
<a name="157" /><span class="Maybe">     157:</span> <span class="f">#</span> <span class="n">define</span> <a href="cpu.c_macros_noref.html#_Q1BVX1ZFQ1RPUl9MSU1JVF8w"><span class="b">CPU_VECTOR_LIMIT</span></a>        <span class="f">(</span><span class="c">64</span> <span class="f">*</span> <a href="cpu.c_macros_ref.html#_TlJfQ1BVU18w"><span class="b">NR_CPUS</span></a><span class="f">)</span>
<a name="158" /><span class="Maybe">     158:</span> <span class="f">#</span> <span class="n">define</span> <a href="cpu.c_macros_noref.html#_TlJfSVJRU18w"><span class="b">NR_IRQS</span></a>                    \
<a name="159" /><span class="Maybe">     159:</span>     <span class="f">(</span><a href="cpu.c_macros_noref.html#_Q1BVX1ZFQ1RPUl9MSU1JVF8w"><span class="b">CPU_VECTOR_LIMIT</span></a> <span class="f">&gt;</span> <a href="cpu.c_macros_noref.html#_SU9fQVBJQ19WRUNUT1JfTElNSVRfMA__"><span class="b">IO_APIC_VECTOR_LIMIT</span></a> <span class="f">?</span>    \
<a name="160" /><span class="Maybe">     160:</span>         <span class="f">(</span><a href="cpu.c_macros_ref.html#_TlJfVkVDVE9SU18w"><span class="b">NR_VECTORS</span></a> <span class="f">+</span> <a href="cpu.c_macros_noref.html#_Q1BVX1ZFQ1RPUl9MSU1JVF8w"><span class="b">CPU_VECTOR_LIMIT</span></a><span class="f">)</span>  <span class="f">:</span>    \
<a name="161" /><span class="Maybe">     161:</span>         <span class="f">(</span><a href="cpu.c_macros_ref.html#_TlJfVkVDVE9SU18w"><span class="b">NR_VECTORS</span></a> <span class="f">+</span> <a href="cpu.c_macros_noref.html#_SU9fQVBJQ19WRUNUT1JfTElNSVRfMA__"><span class="b">IO_APIC_VECTOR_LIMIT</span></a><span class="f">)</span><span class="f">)</span>
<a name="162" /><span class="False">     162:</span> <span class="f">#</span><span class="n">else</span> <span class="k">/* !CONFIG_X86_IO_APIC: */</span>
<a name="163" /><span class="False">     163:</span> <span class="f">#</span> <span class="n">define</span> <a href="cpu.c_macros_noref.html#_TlJfSVJRU18w"><span class="b">NR_IRQS</span></a>            <a href="cpu.c_macros_ref.html#_TlJfSVJRU19MRUdBQ1lfMA__"><span class="b">NR_IRQS_LEGACY</span></a>
<a name="164" /><span class="Maybe">     164:</span> <span class="f">#</span><span class="n">endif</span>
<a name="165" /><span class="Maybe">     165:</span> 
<a name="166" /><span class="True">     166:</span> <span class="f">#</span><span class="n">endif</span> <span class="k">/* _ASM_X86_IRQ_VECTORS_H */</span>
<a name="167" /><span class="True">     167:</span> </pre>
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